<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
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<TD ALIGN=CENTER COLSPAN='4'><B>SynthTest Project Status (06/19/2012 - 15:12:09)</B></TD></TR>
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<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>FAWonFPGA.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
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<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>SynthTest</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>Synthesized</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx75-3csg484</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>
No Errors</TD>
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<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.2</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='E:/Riccardo/Dropbox/Xilinx/faw-on-fpga\_xmsgs/*.xmsgs?&DataKey=Warning'>9 Warnings (0 new)</A></TD>
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<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
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<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
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<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>
<A HREF_DISABLED='C:/Users/User/Documents/progettoVHDL/FAWSinc\SynthTest_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='2'><B>Current Errors</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=CurrentErrors"><B>[-]</B></a></TD></TR>
<TR ALIGN=LEFT BGCOLOR='#FFFF99'><TD COLSPAN='3'><B>No Errors Found</B></TD></TR>
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&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='2'><B>Current Warnings</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=CurrentWarnings"><B>[-]</B></a></TD></TR>
<TR ALIGN=LEFT BGCOLOR='#FFFF99'><TD><B>Synthesis Warnings</B></TD><TD COLSPAN='2'><B>New</B></TD></TR>
<TR ALIGN=LEFT><TD>WARNING:Xst:1710: - FF/Latch &lt;oe_tcpsr[3]_clk_tcpsr_DFF_2867&gt; (without init value) has a constant value of 0 in block &lt;TCP_ShiftRegister_1&gt;. This FF/Latch will be trimmed during the optimization process.</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>WARNING:Xst:1710: - FF/Latch &lt;oe_tcpsr[4]_clk_tcpsr_DFF_2859&gt; (without init value) has a constant value of 0 in block &lt;TCP_ShiftRegister_1&gt;. This FF/Latch will be trimmed during the optimization process.</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>WARNING:Xst:1710: - FF/Latch &lt;oe_tcpsr[0]_clk_tcpsr_DFF_2891&gt; (without init value) has a constant value of 0 in block &lt;TCP_ShiftRegister_1&gt;. This FF/Latch will be trimmed during the optimization process.</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>WARNING:Xst:1710: - FF/Latch &lt;oe_tcpsr[2]_clk_tcpsr_DFF_2875&gt; (without init value) has a constant value of 0 in block &lt;TCP_ShiftRegister_1&gt;. This FF/Latch will be trimmed during the optimization process.</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>WARNING:Xst:1710: - FF/Latch &lt;oe_tcpsr[1]_clk_tcpsr_DFF_2883&gt; (without init value) has a constant value of 0 in block &lt;TCP_ShiftRegister_1&gt;. This FF/Latch will be trimmed during the optimization process.</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>WARNING:Xst:1710: - FF/Latch &lt;oe_tcpsr[4]_clk_tcpsr_DFF_2859&gt; (without init value) has a constant value of 0 in block &lt;TCP_ShiftRegister&gt;. This FF/Latch will be trimmed during the optimization process.</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>WARNING:Xst:3002: - This design contains one or more registers/latches that are directly incompatible with the Spartan6 architecture. The two primary causes of this is either a register or latch described with both an asynchronous set and asynchronous reset, or a register or latch described with an asynchronous set or reset which however has an initialization value of the opposite polarity (i.e. asynchronous reset with an initialization value of 1). While this circuit can be built, it creates a sub-optimal implementation in terms of area, power and performance. For a more optimal implementation Xilinx highly recommends one of the following: 1) Remove either the set or reset from all registers and latches if not needed for required functionality 2) Modify the code in order to produce a synchronous set and/or reset (both is preferred) 3) Ensure all registers have the same initialization value as the described asynchronous set or reset polarity 4) Use the -async_to_sync option to transform the asynchronous set/reset to synchronous operation (timing simulation highly recommended when using this option)</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>WARNING:Xst:2254: - Area constraint could not be met for block &lt;SynthTest&gt;, final ratio is 227.</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>WARNING:Xst:1336: - (*) More than 100% of Device resources are used</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
<TD ALIGN=RIGHT>64598</TD>
<TD ALIGN=RIGHT>93296</TD>
<TD ALIGN=RIGHT COLSPAN='2'>69%</TD>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>16560</TD>
<TD ALIGN=RIGHT>46648</TD>
<TD ALIGN=RIGHT COLSPAN='2'>35%</TD>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>81158</TD>
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD>
<TD ALIGN=RIGHT>51308</TD>
<TD ALIGN=RIGHT>328</TD>
<TD ALIGN=RIGHT COLSPAN='2'>15642%</TD>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Block RAM/FIFO</TD>
<TD ALIGN=RIGHT>9</TD>
<TD ALIGN=RIGHT>172</TD>
<TD ALIGN=RIGHT COLSPAN='2'>5%</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGCTRLs</TD>
<TD ALIGN=RIGHT>9</TD>
<TD ALIGN=RIGHT>16</TD>
<TD ALIGN=RIGHT COLSPAN='2'>56%</TD>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='E:/Riccardo/Dropbox/Xilinx/faw-on-fpga\SynthTest.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Tue 19. Jun 15:12:08 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='E:/Riccardo/Dropbox/Xilinx/faw-on-fpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>9 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='E:/Riccardo/Dropbox/Xilinx/faw-on-fpga\_xmsgs/xst.xmsgs?&DataKey=Info'>6 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='E:/Riccardo/Dropbox/Xilinx/faw-on-fpga\isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Tue 19. Jun 14:54:47 2012</TD></TR>
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<br><center><b>Date Generated:</b> 06/19/2012 - 15:12:09</center>
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